Interconnect line selectively isolated from an underlying contact plug

Patent metadata

Field	Value
Publication number	US-9123786-B2
Application number	US-201414319284-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 16, 2000
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A processor-based system, comprising:
a processor; and
a memory device connected to said processor, said memory device comprising:
a first conductive stud and a second conductive stud;
a bit line over and in electrical contact with said first conductive stud, wherein said bit line also overlies a portion of said second conductive stud without making electrical contact to the seco…

Assignees

• Micron Technology Inc

Inventors

• Drynan John M

Classifications

• H10W20/077

  Electricity · mapped topic

• H10W20/076

  Electricity · mapped topic

• H10W20/20

  Electricity · mapped topic

• H10W20/063 Primary

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic