Semiconductor device and method of manufacturing same
US-2024395697-A1 · Nov 28, 2024 · US
Memory process and memory structure made thereby
US9123784B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123784-B2 |
| Application number | US-201213590204-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 21, 2012 |
| Priority date | Aug 21, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory structure, comprising: a substrate, having therein a plurality of trenches, and having thereon an array area and a contact area apart from the array area, wherein each trench has a first portion in the contact area and a second portion in the array area, and the substrate between the first portions of the trenches is also in the contact area and has a surface lower than a surface of the substrate between the trenches outside of the contact area; a…
Assignees
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Classifications
Electricity · mapped topic
- H10W20/056Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9123784B2 cover?
- A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrat…
- Who is the assignee on this patent?
- Gopalan Vivek, Kerr Robert, Tsai Hung-Ming, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/056. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).