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Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
US9123783B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123783-B2 |
| Application number | US-201213673549-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 9, 2012 |
| Priority date | Nov 9, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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- Title
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Abstract
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Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming an integrated circuit, the method comprising: providing a base substrate having an embedded electrical contact disposed therein; forming an interlayer dielectric overlying the base substrate; etching a recess through the interlayer dielectric over the embedded electrical contact with a surface of the embedded electrical contact exposed in the recess; forming a protecting liner in the recess and over the exposed surface of the embedd…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/035Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9123783B2 cover?
- Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A…
- Who is the assignee on this patent?
- Globalfoundries Inc, Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W20/035. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).