Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Semiconductor device and production method therefor
US9123779B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123779-B2 |
| Application number | US-201414291551-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2014 |
| Priority date | Jun 4, 2013 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is provided, and a production method for the semiconductor device. In the production method, forming each of the interconnection layers of the multi-level interconnection structure includes: forming a real interconnection and a dummy interconnection, forming an insulative film covering the real interconnection and the dummy interconnection, and planarizing a surface of the insulative film. The production method may include computing an in-plane distribution of an overall thickness of the multi-level interconnection structure to be expected when no dummy interconnection is formed; and defining a dummy present zone and a dummy absent zone. The dummy interconnection is formed in the defined dummy present zone outside the defined dummy absent zone in each of the interconnection layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A production method for a semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate, the method comprising: an interconnection layer forming step of forming each of the interconnection layers of the multi-level interconnection structure, the interconnection layer forming step including an interconnection forming step of forming a real interconnection…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10W20/092Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/43Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9123779B2 cover?
- A semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is provided, and a production method for the semiconductor device. In the production method, forming each of the interconnection layers of the multi-level interconnection structure includes: forming a real interconnection and a…
- Who is the assignee on this patent?
- Rohm Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/092. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).