Damascene conductor for 3D array

Patent metadata

Field	Value
Publication number	US-9123778-B2
Application number	US-201313897702-A
Country	US
Kind code	B2
Filing date	May 20, 2013
Priority date	Mar 13, 2013
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

First claim

What is claimed is:

1. A method of forming a conductor structure for a device, comprising:
providing a substrate having a plurality of spaced apart stacks of semiconductor strips;
forming a fill material having a plurality of patterned trenches between and over the plurality of spaced apart stacks; and
filling the plurality of patterned trenches with a conductor material to form conductive lines overlying the plurality of spaced apart stacks of semiconductor strips disposed or…

Assignees

• Macronix Int Co Ltd

Inventors

• Lai Erh-Kun
• Shih Yen-Hao
• Lee Guanru

Classifications

• H10W20/074

  Electricity · mapped topic

• H10W20/072

  Electricity · mapped topic

• H10W20/46

  Electricity · mapped topic

• H10W20/085 Primary

  Electricity · mapped topic

• H10D64/685

  Electricity · mapped topic