Method for manufacturing semiconductor device

US9123751B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9123751-B2
Application numberUS-201414287494-A
CountryUS
Kind codeB2
Filing dateMay 27, 2014
Priority dateOct 24, 2008
Publication dateSep 1, 2015
Grant dateSep 1, 2015

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a semiconductor device, comprising: forming a gate electrode layer over a substrate having an insulating surface; stacking a gate insulating layer, an oxide semiconductor film, and a conductive film over the gate electrode layer; forming a first mask layer over the gate insulating layer, the oxide semiconductor film, and the conductive film; performing a first etching with the first mask layer to etch the oxide semiconductor…

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What does patent US9123751B2 cover?
An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive f…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D99/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).