Vertical type semiconductor devices and methods of manufacturing the same
US-2024172441-A1 · May 23, 2024 · US
Method of manufacturing a semiconductor device
US9123748B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123748-B2 |
| Application number | US-201414567810-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 11, 2014 |
| Priority date | May 2, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
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A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming first sacrificial layers and second sacrificial layers alternately with each other; forming channel holes by etching the first sacrificial layers and the second sacrificial layers; forming a floating gate material layer, a tunnel insulating layer, and a channel layer in the channel holes; forming slits by etching the first sacrificial layers and the second sacrificial laye…
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Physics · mapped topic
- H10D30/689Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9123748B2 cover?
- A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed betwee…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/689. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).