Semiconductor memory device
US-2024334693-A1 · Oct 3, 2024 · US
Nonvolatile semiconductor memory device and manufacturing method thereof
US9123747B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123747-B2 |
| Application number | US-201414195022-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 3, 2014 |
| Priority date | Aug 9, 2013 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
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According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-type semiconductor in which boron is doped, and the second polysilicon region is an n-type semiconductor in which phosphorus and boron are doped.
First claim
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What is claimed is: 1. A nonvolatile semiconductor memory device comprising: memory cell transistors including a floating gate and a control gate; and a peripheral circuit transistor including a lower electrode and an upper electrode, wherein the floating gate includes a first polysilicon region that includes a p-type semiconductor that is doped with boron, the lower electrode includes a second polysilicon region that includes an n-type semiconductor, the second polysilicon r…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/0411Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9123747B2 cover?
- According to one embodiment, a plurality of memory cell transistors including a floating gate and a control gate and a plurality of peripheral circuit transistors including a lower electrode portion and an upper electrode portion are included. The floating gate includes a first polysilicon region, and the lower electrode includes a second polysilicon region. The first polysilicon region is a p-…
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).