High electron mobility transistor and method for forming the same
US-12176414-B2 · Dec 24, 2024 · US
Metamorphic growth of III-V semiconductor on silicon substrate by MOCVD for high speed III-V transistors
US9123741B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123741-B2 |
| Application number | US-201313752971-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 29, 2013 |
| Priority date | Jan 29, 2013 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A III-V semiconductor device on a silicon substrate is constructed with a silicon (Si) substrate onto which gallium arsenide (GaAs) indium phosphide (InP) and aluminum indium arsenide (AlInAs) to form a structure of AlInAs over InP over GaAs over Si. The GaAs is applied in at least one layer over the Si, followed by at least one layer of InP and at least one layer of AlInAs. A portion of the structure is doped and a cap or passivation layer is applied.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a III-V semiconductor device on a silicon substrate, the method comprising: preparing a silicon (Si) substrate; treating the substrate to form a stable As—Si prelayer on the substrate; applying at least one III/V semiconductor layer comprising a layer of gallium arsenide (GaAs) forming a thin strain GaInAs layer; applying at least one layer of a second III/V semiconductor material comprising a layer of indium phosphide (InP…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9123741B2 cover?
- A III-V semiconductor device on a silicon substrate is constructed with a silicon (Si) substrate onto which gallium arsenide (GaAs) indium phosphide (InP) and aluminum indium arsenide (AlInAs) to form a structure of AlInAs over InP over GaAs over Si. The GaAs is applied in at least one layer over the Si, followed by at least one layer of InP and at least one layer of AlInAs. A portion of the st…
- Who is the assignee on this patent?
- Nano & Advanced Materials Inst Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/015. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).