Semiconductor device and method for forming the same
US-2015001604-A1 · Jan 1, 2015 · US
Semiconductor device and method of manufacturing the same
US9123736B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123736-B2 |
| Application number | US-201414564761-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 9, 2014 |
| Priority date | Aug 30, 2011 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
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The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.
First claim
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What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a cell region and a peripheral circuit region defined therein; forming gate lines spaced apart from each other over the semiconductor substrate in the cell region; forming an interlayer insulating layer over the semiconductor substrate to cover the entirety of the gate lines; forming first contact holes spaced apart from each other in the…
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Frequently asked questions
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- What does patent US9123736B2 cover?
- The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the int…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D1/716. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).