Airgap interconnect with hood layer and method of forming

Patent metadata

Field	Value
Publication number	US-9123727-B2
Application number	US-201113997171-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a dielectric layer with a plurality of interconnects formed therein, wherein each interconnect has a top surface and a side surface;
an airgap located between adjacent interconnects; and
a plurality of conductive hood layers, wherein each hood layer contacts at least a portion of each of the top surface and the side surface of a corresponding one of the adjacent interconnects.

2.…

Assignees

• Fischer Kevin
• Intel Corp

Inventors

• Fischer Kevin

Classifications

• H10W20/495 Primary

  Electricity · mapped topic

• H10W20/077

  Electricity · mapped topic

• H10W20/072

  Electricity · mapped topic

• H10W20/47

  Electricity · mapped topic

• H10W20/46

  Electricity · mapped topic