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Selective local metal cap layer formation for improved electromigration behavior
US9123726B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123726-B2 |
| Application number | US-201313964772-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 12, 2013 |
| Priority date | Jan 18, 2013 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Abstract
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A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method of forming a wiring structure for an integrated circuit device, the method comprising: forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; forming a sacrificial hardmask layer over the ILD layer and first and second metal lines; patterning and removing portions of the sacrificial hardmask layer, thereby masking selected regions of the first…
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Classifications
Electricity · mapped topic
- H10W20/425Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9123726B2 cover?
- A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at peri…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).