Semiconductor constructions and methods of forming interconnects

Patent metadata

Field	Value
Publication number	US-9123722-B2
Application number	US-201414177030-A
Country	US
Kind code	B2
Filing date	Feb 10, 2014
Priority date	Aug 17, 2011
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

First claim

We claim:

1. A semiconductor construction, comprising:
a first level of circuitry;
a first dielectric region over the first level of circuitry;
a second level of circuitry over the first level of circuitry, the second level comprising a pattern of repeating electrically conductive features and comprising an opening through the pattern, the electrically conductive features being disposed laterally outward on both sides of the opening;
a second dielectric region over the secon…

Assignees

• Micron Technology Inc

Inventors

• Yang Ming-Chuan
• Liu Zengtao T
• Sipani Vishal

Classifications

• H10W20/063 Primary

  Electricity · mapped topic

• H10W20/42 Primary

  Electricity · mapped topic

• H01L21/76885

  Electricity · mapped topic

• H01L23/5226 Primary

  Electricity · mapped topic