Semiconductor device and method of manufacturing the same

US9123720B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9123720-B2
Application numberUS-201313950442-A
CountryUS
Kind codeB2
Filing dateJul 25, 2013
Priority dateOct 25, 2012
Publication dateSep 1, 2015
Grant dateSep 1, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles; and an embedded film in the contact hole. 2. The device according to claim 1 , wherein an aspect ratio (depth/diameter) of the contact hole is not smaller than 2. 3. The device according to claim 1 , wherein the catalyst metal is metal or alloy containing one or more elements selected from a group including Co, Ni, and Fe. 4. The device according to claim 1 , wherein an average thickness of the catalyst metal film is not less than 5 nm and not more than 20 nm. 5. The device according to claim 1 , wherein a metal film, an alloy film, or a metal nitride film containing one or more elements selected from a group including Ti, Ta, Mn, Mo, V, Ru, and Cu is provided between the catalyst metal film and the interlayer insulating film.

Assignees

Inventors

Classifications

  • Physical vapour deposition [PVD] · CPC title

  • Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

  • of nanotubes or nanowires · CPC title

  • Carbon or carbon-containing materials, e.g. graphene · CPC title

  • by selectively depositing, e.g. by using selective CVD or plating · CPC title

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What does patent US9123720B2 cover?
A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole,…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10W20/035. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).