Circuit assembly
US-2024371747-A1 · Nov 7, 2024 · US
US9123719B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123719-B2 |
| Application number | US-201213533280-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 26, 2012 |
| Priority date | Jun 26, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.
Opening claim text (preview).
What is claimed is: 1. A method comprising: fabricating, according to a first value of a design parameter, a first layer comprising first layer metal capacitor traces spaced according to the first value; fabricating, according to a second value of the design parameter, a second layer comprising second layer metal capacitor traces spaced according to the second value and running in a different direction than the first layer metal capacitor traces; and fabricating a first polari…
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