Method of manufacturing semiconductor structure having air gap
US-12132087-B2 · Oct 29, 2024 · US
US9123714B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9123714-B2 |
| Application number | US-201313768934-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 15, 2013 |
| Priority date | Feb 16, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns.
Opening claim text (preview).
What is claimed is: 1. A non-volatile memory system, comprising: a plurality of metal vias, each metal via electrically coupled to a drain region of one of a plurality of groups of non-volatile storage elements; a plurality of layer stack columns extending in a column direction over the plurality of metal vias, each layer stack column includes a metal nucleation line in contact with at least one of the plurality of metal vias, a metal bit line in contact with the metal nucleatio…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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