Metal layer air gap formation

US9123714B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9123714-B2
Application numberUS-201313768934-A
CountryUS
Kind codeB2
Filing dateFeb 15, 2013
Priority dateFeb 16, 2012
Publication dateSep 1, 2015
Grant dateSep 1, 2015

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Abstract

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Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns.

First claim

Opening claim text (preview).

What is claimed is: 1. A non-volatile memory system, comprising: a plurality of metal vias, each metal via electrically coupled to a drain region of one of a plurality of groups of non-volatile storage elements; a plurality of layer stack columns extending in a column direction over the plurality of metal vias, each layer stack column includes a metal nucleation line in contact with at least one of the plurality of metal vias, a metal bit line in contact with the metal nucleatio…

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What does patent US9123714B2 cover?
Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by …
Who is the assignee on this patent?
Sandisk Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/072. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).