Semiconductor devices using air spaces to separate conductive structures and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9123550-B2
Application number	US-201314020252-A
Country	US
Kind code	B2
Filing date	Sep 6, 2013
Priority date	Sep 14, 2012
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

A semiconductor device includes a substrate, a conductive pattern (e.g., a contact plug) on an active region of the substrate and having respective first and second sidewalls on opposite first and second sides of the conductive pattern, and first and second conductive lines (e.g., bit lines) on the substrate on respective ones of the first and second sides of conductive pattern and separated from the respective first and second sidewalls by asymmetric first and second air spaces.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a conductive plug on an active region of the substrate and configured to electrically connect the active region to a storage electrode of a capacitor, the conductive plug having respective first and second sidewalls at opposite first and second sides thereof;
first and second conductive lines on the substrate on respective ones of the first and second sides of conductive plug and separated from the respective first and second sidewalls by asymmetric first and second air spaces;
a first insulating layer covering a sidewall of the first conductive line between the first air space and the first conductive line;
a second insulating layer covering the first sidewall of the conductive plug; and
a third insulating layer covering a sidewall of the second conductive line between the second air space and the second conductive line.

2. The device of claim 1 , wherein the first and second air spaces have different widths.

3. The device of claim 2 , wherein at least one of the first and second air spaces has a non-uniform width.

4. The device of claim 3 , wherein the first air space has a uniform width and wherein the second air space has a non-uniform width.

5. The device of claim 1 , wherein the first and second conductive lines are bit lines.

6. The device of claim 1 , wherein the second sidewall of the conductive plug and the third insulating layer are exposed in the second air space.

7. The device of claim 1 , further comprising a fourth insulating layer covering the second sidewall of the conductive plug.

8. The device of claim 1 , wherein the first and second insulating layers have different thicknesses.

9. The device of claim 1 , wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

10. The device of claim 1 , wherein the conductive plug is one of a plurality of contact plugs arranged in a row along a first direction between the first and second conductive lines and wherein the device further comprises a plurality of insulating patterns, respective ones of which filling spaces between adjacent ones of the contact plugs.

11. A semiconductor device comprising:
a substrate;
first and second conductive lines on the substrate;
a plurality of contact plugs arranged in a row along a first direction between the first and second conductive lines, wherein the first and second conductive lines are separated from respective first and second sidewalls of the contact plugs by asymmetric first and second air spaces; and
a plurality of insulating patterns, respective ones of which fill spaces between adjacent ones of the contact plugs,
wherein the plurality of contact plugs and the plurality of insulating patterns have different widths in a second direction perpendicular to the first direction.

12. The device of claim 11 , wherein the first and second air spaces extend along the first direction to separate the plurality of contact plugs from the first and second conductive lines.

13. The device of claim 12 , wherein the first air space has a first width between the first conductive line and the plurality of contact plugs and a second width greater than the first width between the first conductive line and the plurality of insulating patterns.

14. The device of claim 12 , wherein the second air space has a first width between the second conductive line and the plurality of contact plugs and a second width greater than the first width between the second conductive line and the plurality of insulating patterns.

15. The device of claim 12 , wherein the plurality of contact plugs and the plurality of insulating patterns have the same width.

16. A semiconductor device comprising:
a substrate;
first and second conductive bit lines disposed on the substrate and extending along a first direction; and
a plurality of contact plugs disposed between the first and second conductive bit lines and separated therefrom by asymmetrical first and second air spaces, the conductive plugs configured to electrically connect active regions of the substrate to storage electrodes of capacitors.

17. The device of claim 16 , wherein at least one of the first and second air spaces has an irregular width along a lengthwise direction thereof.

18. The device of claim 16 , further comprising a first insulating layer covering sidewalls of the plurality of contact plugs facing the first air space.

19. The device of claim 16 , further comprising a second insulating layer covering sidewalls of the plurality of contact plugs facing the second air space.

Assignees

• Son Nak-Jin
• Samsung Electronics Co Ltd

Inventors

• Son Nak-Jin

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title