Stress migration mitigation

Patent metadata

Field	Value
Publication number	US-9122829-B2
Application number	US-201313956044-A
Country	US
Kind code	B2
Filing date	Jul 31, 2013
Priority date	Jul 31, 2013
Publication date	Sep 1, 2015
Grant date	Sep 1, 2015

Abstract

A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.

First claim

The invention claimed is:

1. A computer-implemented method of configuring a semiconductor device, the method comprising:
identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device; and
placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect;
wherein each segment has a length no greater than the stress-induced vo…

Assignees

• Reber Douglas M
• Shroff Mehul D
• Travis Edward O
• Freescale Semiconductor Inc

Inventors

• Reber Douglas M
• Shroff Mehul D
• Travis Edward O

Classifications

• H10W20/43

  Electricity · mapped topic

• H10W20/40 Primary

  Electricity · mapped topic

• H10W20/42 Primary

  Electricity · mapped topic

• G06F2119/04

  Physics · mapped topic

• G06F30/392

  Physics · mapped topic