Management of Memory Access by Processors through High Bandwidth Interconnects to Memory Sub-Systems
US-2024372621-A1 · Nov 7, 2024 · US
US9122003B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9122003-B2 |
| Application number | US-201313933511-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 2, 2013 |
| Priority date | Jul 18, 2012 |
| Publication date | Sep 1, 2015 |
| Grant date | Sep 1, 2015 |
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A semiconductor optical device includes a light receiving device; an optical waveguide having a mesa structure, the optical waveguide including first, second, third, and fourth waveguide portions; and a passivation layer provided on a side surface of the light receiving device. The mesa structure in the second waveguide portion has a width increasing along the waveguide axis, and the mesa structure in the third waveguide portion has a width decreasing along the waveguide axis. The second waveguide portion includes first and second regions, the first region being optically coupled to the first waveguide portion and the second region being optically coupled to the third waveguide portion. The passivation layer is provided on side surfaces of the mesa structure in the second region, the third waveguide portion, and the fourth waveguide portion. The mesa structures in the first waveguide portion and the first region have side surfaces without the passivation layer.
Opening claim text (preview).
What is claimed is: 1. A semiconductor optical device, comprising: a light receiving device; an optical waveguide having a mesa structure, the optical waveguide including a first waveguide portion, a second waveguide portion, a third waveguide portion, and a fourth waveguide portion, which are arranged along a waveguide axis; and a passivation layer provided on a side surface of the light receiving device, wherein the second waveguide portion is optically coupled to the firs…
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