Methods of forming stressed fin channel structures for FinFET semiconductor devices

Patent metadata

Field	Value
Publication number	US-9117930-B2
Application number	US-201313960200-A
Country	US
Kind code	B2
Filing date	Aug 6, 2013
Priority date	Aug 6, 2013
Publication date	Aug 25, 2015
Grant date	Aug 25, 2015

Abstract

One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

First claim

What is claimed:

1. A method, comprising:
forming a plurality of fin-formation trenches in a semiconductor substrate, said fin-formation trenches defining a fin having an upper surface;
forming a first stressed conductive material layer within said trenches and above said upper surface of said fin;
forming a second stressed conductive material layer above said first stressed conductive material layer and within said trenches;
performing at least one etching process to remove a portion of said second stressed conductive material layer and a portion of said first stressed conductive material layer that is positioned above said upper surface of said fin while leaving portions of said first stressed conductive material layer positioned within said trenches; and
after performing said at least one etching process, forming a conductive layer above said second stressed conductive material layer, said upper surface of said fin and said portions of said first stressed conductive material layer positioned within said trenches.

2. The method of claim 1 , wherein said first stressed conductive material layer and said second stressed conductive material layer are formed so as to exhibit a first type of stress and a second type of stress, respectively, wherein said second type of stress is opposite to said first type of stress.

3. The method of claim 1 , wherein said first stressed conductive material layer and said second stressed conductive material layer are formed so as to exhibit the same type of stress.

4. The method of claim 3 , wherein said first stressed conductive material layer and said second stressed conductive material layer are formed so as to exhibit different magnitudes of the same type of stress.

5. The method of claim 4 , wherein a difference between said different magnitudes of the same type of stress has an absolute value of at least 300 MPa.

6. The method of claim 1 , wherein said first stressed conductive material layer and said second stressed conductive material layer are comprised of different materials.

7. The method of claim 2 , wherein said first type of stress is a compressive stress and said second type of stress is a tensile stress.

8. The method of claim 1 , wherein said first stressed conductive material layer is a layer of substantially fluorine-free tungsten, tungsten nitride or tungsten carbide and said second stressed conductive material layer is a layer of fluorine-containing tungsten.

9. The method of claim 1 , wherein said conductive layer is a layer of fluorine-containing tungsten.

10. The method of claim 7 , wherein said first stressed conductive material layer is formed so as to have a compressive stress that falls within the range of −1 to −3 GPa and said second stressed conductive material layer is formed so as to have a tensile stress that falls within the range of +1 to +3.5 GPa.

11. The method of claim 1 , wherein, prior to forming said first stressed conductive material layer, the method further comprises:
forming a layer of high-k insulating material on said upper surface of said fin and on sidewalls of said fin; and
forming a layer of work-function adjusting material above said layer of high-k insulating material and wherein forming said first stressed conductive material layer comprises forming said first stressed conductive material layer on said layer of work-function adjusting material.

12. A method, comprising:
forming a plurality of fin-formation trenches in a semiconductor substrate, said fin-formation trenches defining a fin having an upper surface;
forming a layer of high-k insulating material on said upper surface of said fin and on sidewalls of said fin;
forming a layer of work-function adjusting material above said layer of high-k insulating material;
forming a first stressed conductive material layer having a first type of stress on said work-function adjusting material;
forming a second stressed conductive material layer on said first stressed conductive material layer and within said trenches, said second stressed conductive material layer having a second type of stress that is opposite to said first type of stress;
performing at least one etching process to remove a portion of said second stressed conductive material layer and a portion of said first stressed conductive material layer that is positioned above said upper surface of said fin while leaving portions of said first stressed conductive material layer positioned within said trenches; and
after performing said at least one etching process, forming a conductive layer above said second stressed conductive material layer, said upper surface of said fin and said portions of said first stressed conductive material layer positioned within said trenches.

13. The method of claim 12 , wherein said first type of stress is a compressive stress and said second type of stress is a tensile stress.

14. The method of claim 12 , wherein said first stressed conductive material layer is a layer of substantially fluorine-free tungsten, tungsten nitride or tungsten carbide and said second stressed conductive material layer is a layer of fluorine-containing tungsten.

15. The method of claim 12 , wherein said conductive layer is a layer of fluorine-containing tungsten.

16. The method of claim 13 , wherein said first stressed conductive material layer is formed so as to have a compressive stress that falls within the range of −1 to −3. GPa and said second stressed conductive material layer is formed so as to have a tensile stress that falls within the range of +1 to +3.5 GPa.

17. A method, comprising:
forming a plurality of fin-formation trenches in a semiconductor substrate, said fin-formation trenches defining a fin having an upper surface;
forming a layer of high-k insulating material on said upper surface of said fin and on sidewalls of said fin;
forming a layer of work-function adjusting material above said layer of high-k insulating material;
forming a first stressed conductive material layer having a first type of stress on said work-function adjusting material;
forming a second stressed conductive material layer on said first stressed conductive material layer and within said trenches, said second stressed conductive material layer also being formed so as to exhibit said first type of stress;
performing at least one etching process to remove a portion of said second stressed conductive material layer and a portion of said first stressed conductive material layer that is positioned above said upper surface of said fin while leaving portions of said first stressed conductive material layer positioned within said trenches; and
after performing said at least one etching process, forming a conductive layer above said second stressed conductive material layer, said upper surface of said fin and said portions of said first stressed conductive material layer positioned within said trenches.

18. The method of claim 17 , wherein said first stressed conductive material layer and said second stressed conductive material layer are formed so as to exhibit different magnitudes of said first type of stress.

19. The method of claim 18 , wherein a difference between said different magnitudes of the first type of stress has an absolute value of at least 300 MPa.

20. The method of claim 17 , wherein said first type of stress is a tensile stress.

21. The method of claim 17 , wherein said first type of stress is a compressive stress.

22. A method, comprising:
forming a plurality of fin-

Assignees

• Globalfoundries Inc

Inventors

• Kamineni Vimal K
• Deniz Derya
• Bello Abner
• Paul Abhijeet
• Miller Robert J
• Taylor Jr William J

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0193 Primary

  the components including FinFETs · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title