Pre-decoder circuitry
US-2024321327-A1 · Sep 26, 2024 · US
US9117516B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9117516-B2 |
| Application number | US-201314018790-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 5, 2013 |
| Priority date | May 10, 2013 |
| Publication date | Aug 25, 2015 |
| Grant date | Aug 25, 2015 |
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According to one embodiment, a memory includes memory cells between first conductive lines and second conductive lines. A control circuit is configured to apply a first potential to a first end of a selected first conductive line connected to the selected memory cell among the first conductive lines and first ends of unselected second conductive lines not connected to the selected memory cell among the second conductive lines, apply a second potential larger than the first potential to a first end of a selected second conductive line connected to the selected memory cell among the second conductive lines, apply third potentials smaller than the second potential to first ends of unselected first conductive lines not connected to the selected memory cell among the first conductive lines respectively, and change values of the third potentials based on an address of the selected first conductive line.
Opening claim text (preview).
What is claimed is: 1. A resistance change memory comprising: a plurality of first conductive lines extending in a first direction, and arranged side by side in a second direction which intersects the first direction; a plurality of second conductive lines extending in the second direction, and arranged side by side in the first direction; memory cells connected between the first conductive lines and the second conductive lines, at respective intersections of the first conduct…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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