Split gate non-volatile memory (NVM) cell and method therefor

Patent metadata

Field	Value
Publication number	US-9112047-B2
Application number	US-201313779859-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Feb 28, 2013
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar.

First claim

What is claimed is:

1. A split gate memory structure comprising:
a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions, wherein the pillar has a major surface extending between first and the second ends, wherein the major surface exposes the first source/drain region, the channel region, and the second source/drain region;
a select gate adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar;
a charge storage layer adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar; and
a control gate adjacent the charge storage layer, wherein the control gate encircles the pillar and wherein the charge storage layer is between the control gate and the pillar.

2. The split gate memory structure of claim 1 , further comprising a semiconductor layer, wherein the pillar of active region extends substantially vertically from the semiconductor layer.

3. The split gate memory structure of claim 2 , wherein the first source/drain region is in physical contact with the semiconductor layer.

4. The split gate memory structure of claim 1 , wherein the control gate overlaps a portion of the select gate such that the overlapped portion of the select gate is between the control gate and the pillar.

5. The split gate memory structure of claim 4 , wherein the charge storage layer is between the control gate and the overlapped portion of the select gate.

6. The split gate memory structure of claim 1 , further comprising:
a gate dielectric layer between the select gate and the pillar, encircling the first source/drain region and the first portion of the channel region.

7. The split gate memory structure of claim 1 , wherein an average diameter of the pillar is less than or equal to 1000 Angstroms.

8. A split gate memory structure, comprising:
a semiconductor layer;
a pillar on the semiconductor layer and substantially perpendicular to the semiconductor layer, wherein the first pillar has a first source/drain region disposed at a first end of the pillar on the semiconductor layer, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions;
a select gate over the semiconductor layer and adjacent the first source/drain region and a first portion of the channel region;
a charge storage layer adjacent the second source/drain region and a second portion of the channel region above the first portion of the channel region, and over the select gate; and
a control gate adjacent the charge storage layer, the second source/drain region, and the second portion of the channel region and over the select gate.

9. The split gate memory structure of claim 8 , wherein the charge storage layer is between the control gate and the select gate.

10. The split gate memory structure of claim 8 , wherein the select gate is not adjacent the second portion of the channel region and the second source/drain region.

11. The split gate memory structure of claim 8 , wherein the charge storage layer comprises nanocrystals.

12. The split gate memory structure of claim 8 , further comprising:
a gate dielectric layer between the select gate and the pillar.

13. The split gate memory structure of claim 8 , wherein the select gate substantially encircles the first source/drain region and the first portion of the channel region.

14. The split gate memory structure of claim 13 , wherein
the charge storage layer substantially encircles the second source/drain region, the second portion of the channel region, and the select gate; and
the control gate substantially encircles the second source/drain region, the second portion of the channel region, and the select gate, wherein the charge storage layer is between the control gate and the pillar and between the control gate and the select gate.

15. The split gate memory structure of claim 14 , further comprising:
a contact on the second end of the pillar, wherein the control gate substantially encircles the contact.

16. The split gate memory structure of claim 8 , further comprising:
a second pillar on the semiconductor layer and substantially perpendicular to the semiconductor layer, wherein the second pillar is laterally spaced apart from the pillar, and the second pillar has a first source/drain region disposed at a first end of the second pillar on the semiconductor layer, a second source/drain region disposed at a second end of the second pillar, opposite the first end of the second pillar, and a channel region between the first and second source/drain regions of the second pillar;
a second select gate over the semiconductor layer and adjacent the first source/drain region of the second pillar and a first portion of the channel region of the second pillar;
a second charge storage layer adjacent the second source/drain region of the second pillar and a second portion of the channel region of the second pillar above the first portion of the channel region of the second pillar, and over the second select gate; and
a second control gate adjacent the second charge storage layer, the second source/drain region of the second pillar, and the second portion of the channel region of the second pillar and over the second select gate.

17. The split gate memory structure of claim 16 , wherein the select gate is in direct physical contact with the second select gate.

Assignees

• Kang Sung-Taeg
• Hong Cheong Min
• Freescale Semiconductor Inc

Inventors

• Kang Sung-Taeg
• Hong Cheong Min

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/697

  having trapping at multiple separated sites, e.g. multi-particles trapping sites · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title