SOI substrate and method for manufacturing SOI substrate

US9111997B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9111997-B2
Application numberUS-201113339427-A
CountryUS
Kind codeB2
Filing dateDec 29, 2011
Priority dateMar 26, 2007
Publication dateAug 18, 2015
Grant dateAug 18, 2015

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Abstract

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An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a first single crystal silicon substrate to form a second single crystal silicon substrate which has a chip size; a step (B) of forming an insulating layer on one surface of the second single crystal silicon substrate, and forming an embrittlement layer in the second single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the second single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the second single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface, are conducted.

First claim

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What is claimed is: 1. A manufacturing method of an SOI substrate, comprising the steps of: forming an insulating layer on one surface of a first single crystal silicon substrate; forming an embrittlement layer in the first single crystal silicon substrate; cutting the first single crystal silicon substrate to form a plurality of second single crystal silicon substrates each of which has a chip size after the step of forming the embrittlement layer; bonding a substrate havin…

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What does patent US9111997B2 cover?
An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a first single crystal silicon substrate to form a second single crystal silicon substrate which has a chip size; a step (B) of forming an insulating layer on one surface of the second single crystal silico…
Who is the assignee on this patent?
Yamazaki Shunpei, Togawa Maki, Arai Yasuyuki, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P90/1916. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).