Shallow bipolar junction transistor

Patent metadata

Field	Value
Publication number	US-9111985-B1
Application number	US-65278507-A
Country	US
Kind code	B1
Filing date	Jan 11, 2007
Priority date	Jan 11, 2007
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.

First claim

What is claimed is:

1. A shallow bipolar junction transistor comprising:
a high voltage n+ well implanted into a semiconductor substrate;
an oxide nitride oxide (ONO) layer, an n+ collector, and a bit line residual oxide removal (BLROE)/spacer over etch (SPXOE) layer above said high voltage n+ well;
a bit line n+ implant (BNI) above said high voltage n+ well, wherein a portion of said ONO layer is formed around a portion of said BNI;
a plurality of emitters in a central region of the transistor, a base laterally separated from the plurality of emitters, and an n+ core implant surrounding the plurality of emitters to isolate the base and the plurality of emitters, wherein the n+ core implant defines a difference between said base and an emitter;
a high voltage gate oxide (HVGOX) above said n+ collector and around said base; and
a p+ source/drain implant (PP) layer around said base.

2. The shallow bipolar junction transistor of claim 1 wherein said oxide nitride oxide (ONO) layer is at a periphery area of said BNI.

3. The shallow bipolar junction transistor of claim 1 further comprising a shallow trench isolation (STI) region proximate to said ONO layer.

4. The shallow bipolar junction transistor of claim 1 wherein said bit line n+ implant is at a periphery area of said plurality of emitters.

5. The shallow bipolar junction transistor of claim 4 further comprising an n+ implant for isolating a base and emitters of said shallow bipolar junction transistor.

6. The shallow bipolar junction transistor of claim 1 further comprising an emitter wherein a portion of said emitter is operable to operate as a contact.

7. The shallow bipolar junction transistor of claim 6 wherein said portion of said emitter is operable to operate as a contact without a cobalt silicide (CoSi) layer.

Assignees

• Roy Alok Nandini
• Kathawala Gulzar
• Patel Zubin
• Shiraiwa Hidehiko
• Cypress Semiconductor Corp

Inventors

• Roy Alok Nandini
• Kathawala Gulzar
• Patel Zubin
• Shiraiwa Hidehiko

Classifications

• H10D62/133

  Emitter regions of BJTs · CPC title

• H10D64/281

  Base electrodes for bipolar transistors · CPC title

• H10D64/231 Primary

  Emitter or collector electrodes for bipolar transistors · CPC title

• H10D62/114

  PN junction isolations · CPC title

• H10D10/061

  of lateral BJTs  (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041) · CPC title