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US-9410742-B2 · Aug 9, 2016 · US
Substrate processing apparatus and manufacturing method for a semiconductor device
US9111972B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9111972-B2 |
| Application number | US-59328205-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 27, 2005 |
| Priority date | Jul 13, 2004 |
| Publication date | Aug 18, 2015 |
| Grant date | Aug 18, 2015 |
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Abstract
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The sizes required for maintenance are reduced and an occupying floor area is reduced. The substrate processing apparatus contains a load lock chamber 41 and a transfer chamber 24 respectively provided in order from the rear side within a case 11 ; and a processing chamber 53 provided above the load lock chamber 41 for processing wafers 1 . An opening section 27 A, and an opening and closing means 28 A for opening and closing the opening section 27 A are respectively provided in a location at the rear side of the transfer chamber 24 where the load lock chamber 41 is not arranged.
First claim
Opening claim text (preview).
The invention claimed is: 1. A substrate processing apparatus comprising a load lock chamber, a transfer chamber and a maintenance passage provided in order along a length direction from the rear side within a case having a maintenance opening for entry of maintenance personnel into the maintenance passage from outside the case, and a processing chamber provided above the load lock chamber for processing a substrate, wherein an opening section, arranged in a wall isolating the main…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P72/12Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9111972B2 cover?
- The sizes required for maintenance are reduced and an occupying floor area is reduced. The substrate processing apparatus contains a load lock chamber 41 and a transfer chamber 24 respectively provided in order from the rear side within a case 11 ; and a processing chamber 53 provided above the load lock chamber 41 for processing wafers 1 . An opening section 27 A, and an opening and…
- Who is the assignee on this patent?
- Takeshita Mitsunori, Matsuda Tomoyuki, Hirano Mitsuhiro, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10P72/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).