Method for manufacturing semiconductor memory device and semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9111963-B2
Application number	US-201313971139-A
Country	US
Kind code	B2
Filing date	Aug 20, 2013
Priority date	Mar 25, 2013
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a plurality of pillars and a plurality of sidewall films on a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers. The pillars are arranged in a first direction and a second direction intersecting the first direction at different pitches in the first direction and the second direction. The sidewall films are provided on outer circumferential surfaces of the pillars to extend in the first direction to be linked in the first direction and separated in the second direction. The method includes making a slit to divide the stacked body in the second direction by etching the stacked body under a region between the sidewall films adjacent to each other in the second direction using the pillars and the sidewall films as a mask.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a stacked body provided on the substrate, the stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers;
an insulating separation film extending in a first direction to divide the stacked body in a second direction intersecting the first direction, the insulating separation film having a side wall having an unevenness repeated along the first di…

Assignees

• Toshiba Kk

Inventors

• Murakami Sadatoshi

Classifications

• H10D30/693

  Electricity · mapped topic

• H10D30/0413 Primary

  Electricity · mapped topic

• H01L29/66833 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic