Split-gate non-volatile memory cells having improved overlap tolerance

Patent metadata

Field	Value
Publication number	US-9111908-B2
Application number	US-201213448531-A
Country	US
Kind code	B2
Filing date	Apr 17, 2012
Priority date	Mar 21, 2011
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.

First claim

What is claimed is:

1. A split-gate non-volatile memory (NVM) cell, comprising:
a first gate over a substrate, wherein the first gate is formed from a first conductive layer;
a second conductive layer over the first gate;
a dielectric charge storage layer over the second conductive layer and the substrate, wherein the dielectric later charge storage layer overlaps a first sidewall of the first gate; and
a second gate over the dielectric charge storage layer, wherein the seco…

Assignees

• White Ted R
• Chindalore Gowrishankar L
• Winstead Brian A
• Freescale Semiconductor Inc

Inventors

• White Ted R
• Chindalore Gowrishankar L
• Winstead Brian A

Classifications

• H10D64/035

  Electricity · mapped topic

• H10D30/6892

  Electricity · mapped topic

• H10D30/681

  Electricity · mapped topic

• H10D30/6893 Primary

  Electricity · mapped topic

• H01L29/7881

  Electricity · mapped topic