Floating gate structure with high electrostatic discharge performance

Patent metadata

Field	Value
Publication number	US-9111754-B2
Application number	US-65549307-A
Country	US
Kind code	B2
Filing date	Jan 18, 2007
Priority date	Jul 26, 2005
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

Systems and methods for floating gate structures with high electrostatic discharge performance. In one embodiment, a semiconductor structure includes a floating gate device. The floating gate device includes an embedded diode characterized as having less temperature dependence than a Zener diode. The breakdown voltage of the embedded diode is greater than an operating voltage of an associated integrated circuit and a snapback trigger voltage of the embedded diode is lower than a breakdown voltage of the semiconductor structure.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first floating gate, a second floating gate, and a stack structure including a first type of diode and a second type of diode, wherein said first and second floating gates are located on opposite sides of said stack structure, and wherein said stack structure further includes a semiconductor layer of a first doping type and a plurality of semiconductor regions of a second doping type and of a first doping concentration located on and overlaying a top surface of said semiconductor layer and located inside a top surface boundary of said semiconductor layer.

2. A semiconductor structure of claim 1 wherein said first type of diode comprises a p/n type diode.

3. A semiconductor structure of claim 2 wherein said second type of diode comprises a Zener diode.

4. A semiconductor structure of claim 3 wherein said p/n type diode and said Zener diode comprise a common cathode.

5. A semiconductor structure for electrostatic discharge protection comprising:
a plurality of first fingers coupled to an output pad;
a plurality of second fingers interlaced between said first fingers and coupled to a ground pad;
a plurality of floating gates interposed between said first and second fingers; and
wherein said first fingers comprise a stack structure including a first type of diode and a second type of diode, wherein first and second floating gates are located on opposite sides of said stack structure, and wherein said stack structure further includes a semiconductor layer of a first doping type and a plurality of semiconductor regions of a second doping type and of a first doping concentration located on and overlaying a top surface of said semiconductor layer and located inside a top surface boundary of said semiconductor layer.

6. A semiconductor structure of claim 5 wherein said second type of diode comprises a Zener diode.

7. A semiconductor structure of claim 6 wherein said first type of diode comprises a p/n diode.

8. A semiconductor structure of claim 7 wherein said p/n diode comprises a well of anode material.

9. A semiconductor structure of claim 7 wherein said Zener diode and said p/n diode comprise a common cathode.

10. A semiconductor structure comprising:
a circuit for driving an off-chip output;
wherein said circuit comprises a pull-down device, a first floating gate, a second floating gate, and a stack structure including a first type of diode and a second type of diode, wherein said first and second floating gates are located on opposite sides of said stack structure, and wherein said stack structure further includes a semiconductor layer of a first doping type and a plurality of semiconductor regions of a second doping type and of a first doping concentration located on and overlaying a top surface of said semiconductor layer and located inside a top surface boundary of said semiconductor layer.

11. An electrostatic discharge (ESD) protection circuit for an integrated circuit (IC) for providing protection during an ESD event, said circuit comprising:
a current flow control component; and
a current flow direction control component coupled in series to said current flow control component, wherein said current flow direction control component comprises a first floating gate, a second floating gate, and a stack structure including a first type of diode and a second type of diode, wherein said first and second floating gates are located on opposite sides of said stack structure, and wherein said stack structure further includes a semiconductor layer of a first doping type and a plurality of semiconductor regions of a second doping type and of a first doping concentration located on and overlaying a top surface of said semiconductor layer and located inside a top surface boundary of said semiconductor layer.

12. The ESD protection circuit of claim 11 wherein said current flow control component is a transistor.

13. The ESD protection circuit of claim 12 wherein said transistor is a MOSFET.

Assignees

• Demirlioglu Esin Kutlu
• Luo Min-Yih
• Vishay Siliconix

Inventors

• Demirlioglu Esin Kutlu
• Luo Min-Yih

Classifications

• H10D8/25 Primary

  Zener diodes · CPC title

• H10D62/108

  having localised breakdown regions, e.g. built-in avalanching regions  (in self-protected thyristors H10D18/211) · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D89/813 Primary

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title

• H01L2924/00

  Electricity · mapped topic