Transistor characteristic calculation apparatus using large signal equivalent circuit model

Patent metadata

Field	Value
Publication number	US-9111061-B2
Application number	US-201213726859-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Jul 11, 2012
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.

First claim

What is claimed is:

1. A transistor characteristic calculation apparatus using a large signal equivalent circuit model, comprising:
a gate-to-source capacitance connected between a gate terminal and a source terminal;
a gate-to-drain capacitance connected between the gate terminal and a drain terminal;
a parallel circuit connected between the drain terminal and the source terminal and including a transconductance, a drain conductance, and a drain-to-source capacitance; and
a first trap circuit connected between the drain terminal and the source terminal,
wherein the first trap circuit is configured such that a first parallel circuit including a first resistor and a first capacitor, a diode, and a second parallel circuit including a second resistor and a second capacitor are in turn connected in series.

2. The transistor characteristic calculation apparatus using a large signal equivalent circuit model according to claim 1 , wherein the first trap circuit includes a first diode connected between the first parallel circuit and the second parallel circuit in forward polarity, and a second diode connected between the first parallel circuit and the second parallel circuit in opposite polarity and in parallel with the first diode.

3. A transistor characteristic calculation apparatus using a large signal equivalent circuit model, comprising:
a gate-to-source capacitance connected between a gate terminal and a source terminal;
a gate-to-drain capacitance connected between the gate terminal and a drain terminal;
a parallel circuit connected between the drain terminal and the source terminal and including a transconductance, a drain conductance, and a drain-to-source capacitance; and
a second trap circuit connected between the drain terminal and the gate terminal,
wherein the second trap circuit is configured such that a third parallel circuit including a third resistor and a third capacitor, a diode, and a fourth parallel circuit including a fourth resistor and a fourth capacitor are in turn connected in series.

4. The transistor characteristic calculation apparatus using a large signal equivalent circuit model according to claim 3 , further comprising:
a third trap circuit connected between the source terminal and the gate terminal,
wherein the third trap circuit is configured such that a fifth parallel circuit including a fifth resistor and a fifth capacitor, a diode, and a sixth parallel circuit including a sixth resistor and a sixth capacitor are in turn connected in series.

5. The transistor characteristic calculation apparatus using a large signal equivalent circuit model according to claim 3 , further comprising:
a first trap circuit connected between the drain terminal and the source terminal,
wherein the first trap circuit is configured such that a first parallel circuit including a first resistor and a first capacitor, a diode, and a second parallel circuit including a second resistor and a second capacitor are in turn connected in series.

Assignees

• Otsuka Hiroshi
• Oishi Toshiyuki
• Yamaguchi Yutaro
• Kosaka Naoki
• Miwa Shinichi
• Yamanaka Koji
• Mitsubishi Electric Corp

Inventors

• Otsuka Hiroshi
• Oishi Toshiyuki
• Yamaguchi Yutaro
• Kosaka Naoki
• Miwa Shinichi
• Yamanaka Koji

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5036

  Physics · mapped topic

• G06F17/5068 Primary

  Physics · mapped topic