Data processing array interface having interface tiles with multiple direct memory access circuits
US-12164451-B2 · Dec 10, 2024 · US
US9110885B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9110885-B2 |
| Application number | US-21291708-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 18, 2008 |
| Priority date | Sep 18, 2008 |
| Publication date | Aug 18, 2015 |
| Grant date | Aug 18, 2015 |
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A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
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What is claimed is: 1. A method of performing cache injection, comprising: executing a cache injection instruction, wherein the cache injection instruction has an associated address and the cache injection instruction indicates that cache injection is to be employed to provide input/output data to a data block of a cache at the associated address; monitoring, by the cache, addresses on a bus in response to the execution of the cache injection instruction; and acquiring, at the…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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