Techniques for cache injection in a processor system

US9110885B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9110885-B2
Application numberUS-21291708-A
CountryUS
Kind codeB2
Filing dateSep 18, 2008
Priority dateSep 18, 2008
Publication dateAug 18, 2015
Grant dateAug 18, 2015

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Abstract

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A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.

First claim

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What is claimed is: 1. A method of performing cache injection, comprising: executing a cache injection instruction, wherein the cache injection instruction has an associated address and the cache injection instruction indicates that cache injection is to be employed to provide input/output data to a data block of a cache at the associated address; monitoring, by the cache, addresses on a bus in response to the execution of the cache injection instruction; and acquiring, at the…

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What does patent US9110885B2 cover?
A technique for performing cache injection includes monitoring addresses on a bus. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
Who is the assignee on this patent?
Arimilli Lakshminarayana B, Arimilli Ravi K, Sinharoy Balaram, and 1 more
What technology area does this patent fall under?
Primary CPC classification G06F13/28. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).