Dynamic allocation of heterogenous memory in a computing system

Patent metadata

Field	Value
Publication number	US-9110592-B2
Application number	US-201313758613-A
Country	US
Kind code	B2
Filing date	Feb 4, 2013
Priority date	Feb 4, 2013
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A method of operating a computing device includes dynamically managing at least two types of memory based on workloads, or requests from different types of applications. A first type of memory may be high performance memory that may have a higher bandwidth, lower memory latency and/or lower power consumption than a second type of memory in the computing device. In an embodiment, the computing device includes a system on a chip (SoC) that includes Wide I/O DRAM positioned with one or more processor cores. A Low Power Double Data Rate 3 dynamic random access memory (LPDDR3 DRAM) memory is externally connected to the SoC or is an embedded part of the SoC. In embodiments, the computing device may be included in at least a cell phone, mobile device, embedded system, video game, media console, laptop computer, desktop computer, server and/or datacenter.

First claim

What is claimed is:

1. A method performed by a computing system to allocate a type of integrated circuit memory within the computing system to an application processed by a processor within the computing system, the method comprising:
determining types of integrated circuit memory available for the application in the computing system, wherein the types of integrated circuit memory available include a first type of integrated circuit memory and a second type of integrated circuit memory;
receiving a request from the application to use the first type of integrated circuit memory; and
allocating the first type of integrated circuit memory to be used by the application in response to the request from the application.

2. The method of claim 1 , wherein the first type of integrated circuit memory has at least one or more performance characteristics that is better than the second type of integrated circuit memory.

3. The method of claim 1 , wherein the first type of integrated circuit memory has at least one of a higher bandwidth, lower memory latency or lower power consumption than the second type of integrated circuit memory.

4. The method of claim 1 , wherein the determining includes accessing performance characteristics of the first and second types of integrated circuit memory from a list of memory performance characteristics.

5. The method of claim 4 , wherein the list of performance characteristics is obtained via the Internet, and wherein the list of performance characteristics is stored in a processor readable format.

6. The method of claim 1 , wherein the receiving includes reading attribute information on an application manifest that indicates the request from the application includes a request to use the first type of integrated circuit memory.

7. The method of claim 1 , wherein the allocating includes transferring the request to at least one of a virtual memory allocator or physical memory allocator of a memory controller that manages the allocation of memory pages to physical memory areas in the computing device.

8. The method of claim 1 , further comprising monitoring a memory location and usage of the application at the first type of integrated circuit memory.

9. The method of claim 1 , further comprising comparing the application with a stored list of applications in the computing device, and allocating the first type of integrated circuit memory is replaced with allocating the second type of integrated circuit memory to be used by the application in response to the application being on the stored list, and
wherein the allocating the first type of integrated circuit memory is replaced with allocating the second type of integrated circuit memory to be used by the application when the application usage will exceed physical memory space of the first type of integrated circuit memory.

10. The method of claim 1 , further comprising allocating the first type of integrated circuit memory as cache memory accessible by the application.

11. The method of claim 1 , wherein the determining includes initiating a request to the first and second types of integrated circuit memory for information regarding the integrated circuit memory, wherein the information regarding the integrated circuit memory is selected from one of memory configuration or power management.

12. An apparatus comprising;
one or more processors;
a first processor readable memory having a first performance characteristic;
a second processor readable memory having a second performance characteristic, wherein the first performance characteristic is better than the second performance characteristic;
one or more software applications; and
an operating system including processor readable instructions, wherein the one or more processors execute the processor readable instructions of the operating system to:
determine whether one or more software applications request usage of the first processor readable memory,
determine an amount of processor readable memory the one or more software applications uses, and
allow at least one of the one or more software applications access to the first processor readable memory in response to the request for usage of the first processor readable memory and the amount of processor readable memory the one or more software applications uses.

13. The apparatus of claim 12 , wherein the first and second performance characteristics are selected from one of bandwidth, memory latency or power consumption.

14. The apparatus of claim 12 , wherein the one or more processors and first processor readable memory are integrated into a single semiconductor die housed by a first package, and wherein the second processor readable memory is included in a second semiconductor die housed by a second package.

15. The apparatus of claim 12 , wherein the one or more processors are included on a first semiconductor die and the first processor readable memory is included on a second semiconductor die, wherein the first and second dies are housed by a first package, and wherein the second processor readable memory is included in a third semiconductor die housed by a second package.

16. One or more processor readable memory devices having instructions encoded thereon which when executed cause one or more processors to perform a method for allocating high performance memory to an application software program, the method comprising:
receiving a request from application software program to use the high performance memory;
receiving an amount of memory the application software program uses;
determining an amount of high performance memory that is available; and
allocating the high performance memory to the application software program in response to the amount of memory the application software program uses and the amount of high performance memory that is available.

17. The one or more processor readable memory devices of claim 16 , further comprising allocating memory that is not the high performance memory to the application software program when the amount of memory the application software program uses exceeds the amount of the high performance memory available.

18. The one or more processor readable memory devices of claim 17 , wherein the high performance memory has one of a greater bandwidth, lower memory latency or lower power consumption than the memory that is not the high performance memory.

19. The one or more processor readable memory devices of claim 18 , wherein receiving a request includes reading attribute information on a manifest of the application software program.

20. The one or more processor readable memory devices of claim 19 , further comprising monitoring the high performance memory and the memory that is not the high performance for at least one of health, performance or configuration.

Assignees

• Microsoft Corp
• Microsoft Technology Licensing Llc

Inventors

• Lee Brian
• Tremblay Marc
• Bond Barry
• Sadovsky Vlad
• Ramberg Mark John

Classifications

• G06F9/5016 Primary

  the resource being the memory · CPC title

• G06F2209/501

  Performance criteria · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title