Temperature dependent biasing for leakage power reduction

US9110484B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9110484-B2
Application numberUS-201314035704-A
CountryUS
Kind codeB2
Filing dateSep 24, 2013
Priority dateSep 24, 2013
Publication dateAug 18, 2015
Grant dateAug 18, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device, comprising: a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device, wherein a magnitude of the voltage increases in response to an increase in the temperature of the semiconductor device, and wherein the magnitude of the voltage decreases in response to the temperature of the semiconductor device decreasing; and a logic circuit operably coupled to the biasing ci…

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What does patent US9110484B2 cover?
Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, …
Who is the assignee on this patent?
Freescale Semiconductor Inc
What technology area does this patent fall under?
Primary CPC classification H03K17/145. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).