Flip-flop circuit having a reduced hold time requirement for a scan input

Patent metadata

Field	Value
Publication number	US-9110141-B2
Application number	US-201213668143-A
Country	US
Kind code	B2
Filing date	Nov 2, 2012
Priority date	Nov 2, 2012
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

First claim

What is claimed is:

1. A scan flip-flop circuit, comprising:
a scan input sub-circuit configured to:
receive a scan input signal and a scan enable signal; and
when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels,
wherein the scan input sub-circuit comprises a first stack sub-circuit comprising a first transistor coupled in series with a second transistor, a gate of the first transistor and a gate of the second transistor are coupled to the scan input signal, and the first stack sub-circuit is configured to pull a first signal of the complementary scan input signals to a high logic level when the scan enable signal is asserted and the scan input signal is negated; and

a selection sub-circuit that is coupled to the scan input sub-circuit and configured to:
receive the complementary scan input signals; and
based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a selected input signal.

2. The scan flip-flop circuit of claim 1 , further comprising a storage sub-circuit configured to store the selected input signal and transfer the selected input signal to an output signal when a buffered clock signal transitions between the two different logic levels.

3. The scan flip-flop circuit of claim 2 , further comprising a clock driver configured to receive the clock input signal, generate an inverted clock signal, and generate a buffered clock signal.

4. The scan flip-flop circuit of claim 3 , wherein the clock driver is coupled to a second scan flip-flop circuit that is configured to receive the inverted clock signal and the buffered clock signal, the second scan flip-flop circuit comprising a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions between the two different logic levels.

5. The scan flip-flop circuit of claim 1 , wherein the first stack sub-circuit further comprises a third transistor coupled in series with the first transistor and the second transistor, and a gate of the third transistor is coupled to the scan input signal.

6. The scan flip-flop circuit of claim 1 , wherein the scan input sub-circuit further comprises a second stack sub-circuit comprising a third transistor coupled in series with a fourth transistor, wherein a gate of the third transistor and a gate of the fourth transistor are coupled to the scan input signal, wherein the second stack sub-circuit is configured to pull a second signal of the complementary scan input signals to a low logic level when the scan enable signal is asserted and the scan input signal is asserted.

7. The scan flip-flop circuit of claim 6 , wherein the second stack sub-circuit further comprises a fifth transistor coupled in series with the third and the fourth transistor, and a gate of the fifth transistor is coupled to the scan input signal.

8. The scan flip-flop circuit of claim 6 , wherein a first node between the first transistor and the second transistor is coupled to a second node between the third transistor and the fourth transistor.

9. The scan flip-flop circuit of claim 8 , wherein a connection between the first node and the second node is routed in a metal layer through a first via coupled to the first node and a second via coupled to the second node.

10. The scan flip-flop circuit of claim 5 , wherein a channel length of the first transistor and the second transistor is greater than a channel length of the third transistor.

11. The scan flip-flop circuit of claim 1 , further comprising a scan enable buffer configured to receive the scan enable signal and generate an inverted scan enable signal.

12. The scan flip-flop circuit of claim 11 , wherein the scan enable buffer is coupled to a second flip-flop circuit that is configured to receive the scan enable signal and the inverted scan enable signal, the second flip-flop circuit comprising a second scan input sub-circuit.

13. A scan flip-flop circuit, comprising:
a scan input sub-circuit configured to:
receive a scan input signal and a scan enable signal; and
when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels,
wherein the scan input sub-circuit comprises:
a first inverter that receives the scan input signal and generates an inverted scan input signal;
a second inverter that receives the inverted scan input signal and generates a delayed scan input signal; and
a first transistor having a gate configured to receive the delayed scan input signal, the first transistor is configured to pull a first signal of the complementary scan input signals to a high logic level when the scan enable signal is asserted and the scan input signal is negated; and

a selection sub-circuit that is coupled to the scan input sub-circuit and configured to:
receive the complementary scan input signals; and
based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a selected input signal.

14. The scan flip-flop circuit of claim 13 , wherein the scan input sub-circuit further comprises:
a second transistor having a gate configured to receive the delayed scan input signal, wherein the first transistor is configured to pull a second signal of the complementary scan input signals to a low logic level when the scan enable signal is asserted and the scan input signal is asserted.

15. A system comprising:
a scan flip-flop circuit, comprising:
a scan input sub-circuit configured to:
receive a scan input signal and a scan enable signal; and
when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels,
wherein the scan input sub-circuit comprises a first stack sub-circuit comprising a first transistor coupled in series with a second transistor, a gate of the first transistor and a gate of the second transistor are coupled to the scan input signal, and the first stack sub-circuit is configured to pull a first signal of the complementary scan input signals to a high logic level when the scan enable signal is asserted and the scan input signal is negated; and

a selection sub-circuit that is coupled to the scan input sub-circuit and configured to:
receive the complementary scan input signals; and
based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.

16. The system of claim 15 , wherein the scan input sub-circuit further comprises a second stack sub-circuit comprising a third transistor coupled in series with a fourth transistor, wherein a gate of the third transistor and a gate of the fourth transistor are coupled to the scan input signal, wherein the second stack sub-circuit is configured to pull a second signal of the complementary scan input signals to a low logic level when the scan enable signal is asserted and the scan input signal is asserted.

17. The system of claim 16 , wherein a first node between the first transistor and the second transistor is coupled to a second node between the third transistor and the fourth transistor.

Assignees

• Nvidia Corp

Inventors

• Lin Hwong-Kwo
• Yang Ge
• Zhang Xi
• Yu Jiani
• Chu Ting-Hsiang

Classifications

• G01R31/318544

  Scanning methods, algorithms and patterns (G01R31/3183 takes precedence) · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• G01R31/318594

  Timing aspects (clock circuits G01R31/318552) · CPC title

• G01R31/318555

  Control logic · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title