Interposer instrumentation method and apparatus
US-2024133947-A1 · Apr 25, 2024 · US
Scan circuit, semiconductor device, and method for testing semiconductor device
US9110140B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9110140-B2 |
| Application number | US-201314072448-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2013 |
| Priority date | Jan 17, 2013 |
| Publication date | Aug 18, 2015 |
| Grant date | Aug 18, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain.
First claim
Opening claim text (preview).
What is claimed is: 1. A scan circuit comprising: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series, wherein the first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of t…
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- G01R31/318536Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9110140B2 cover?
- A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the…
- Who is the assignee on this patent?
- Fujitsu Semiconductor Ltd, Socionext Inc
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318536. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).