50 Gb/s Ethernet using serializer/deserializer lanes

Patent metadata

Field	Value
Publication number	US-9106570-B2
Application number	US-201414501201-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Jul 16, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Systems, devices, and methods of implementing 50 Gb/s Ethernet using serializer/deserializer lanes are disclosed. One such device includes circuitry operable to provide a media access control (MAC) interface. The MAC interface is associated with a port having a 50 Gb/s link rate. The device also includes circuitry operable to generate Ethernet frames from data received at the MAC interface and circuitry operable to distribute the Ethernet frames across a group of serial/deserializer (SERDES) lanes associated with the port, the group having size N. The device also includes circuitry operable to transmit the distributed Ethernet frames on each of the SERDES lanes at a 50/N Gb/s rate.

First claim

The invention claimed is:

1. A device comprising:
circuitry configured to
function as a media access control (MAC) interface associated with a port having an M Gb/s link rate, M being a value greater than or equal to 10;
generate Ethernet frames from data received at the MAC interface;
distribute the Ethernet frames across a group of serializer/deserializer (SERDES) lanes associated with the port, the group having a size N which is greater than 1; and
transmit the distribut…

Assignees

• Broadcom Corp

Inventors

• Masood Burhan
• Frazier Howard

Classifications

• H04L49/351

  Electricity · mapped topic

• G06F13/00

  Physics · mapped topic

• Y02B60/31

  Cross-Sectional Technologies · mapped topic

• H04L45/44

  Electricity · mapped topic

• H04L49/25 Primary

  Electricity · mapped topic