Deterministic synchronization for transmitting signals between different clock domains

Patent metadata

Field	Value
Publication number	US-9106401-B2
Application number	US-201213529962-A
Country	US
Kind code	B2
Filing date	Jun 21, 2012
Priority date	Jun 21, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

One embodiment sets forth a technique for deterministic synchronization of signals that are transmitted between different clock domains. The relative phase difference between a source clock domain and a destination clock domain is characterized and the source clock and/or the destination clock are delayed as needed to generate phase-shifted versions of the source and destination clocks for use during a deterministic operating mode. The phase-shifted versions of the source and destination clocks are non-overlapping, meaning that the rising edge of the destination clock does not occur when the source clock is asserted. The non-overlapping source and destination clocks are used by a deterministic synchronization unit to ensure that signals being transmitting from the source clock domain to the destination clock domain are not sampled within a metastability window.

First claim

The invention claimed is:

1. A method for transmitting a first signal between a first clock domain and a second clock domain, the method comprising:
determining a relative phase difference between a source clock of the first clock domain and a destination clock of the second clock domain, wherein the destination clock is not derived from the source clock, and wherein the relative phase difference is measured for different combinations of delay configurations of the source clock an…

Assignees

• Alfieri Robert A
• Nvidia Corp

Inventors

• Alfieri Robert A

Classifications

• H04L7/02

  Electricity · mapped topic

• H04L7/0337 Primary

  Electricity · mapped topic