Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions
US-2024319762-A1 · Sep 26, 2024 · US
US9106329B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9106329-B2 |
| Application number | US-201213349538-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 12, 2012 |
| Priority date | Jan 31, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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A semiconductor chip comprises an internal clock circuit, a first phase shift device, a second phase shift device, a multiplexer, a first output pad, and a controllable pad. The internal clock circuit generates an internal clock signal. The first phase shift device shifts the phase of an external clock signal and outputs a phase shifting clock signal. The multiplexer selectively outputs one of the internal clock signal and the phase shifting clock signal to be a first clock signal. The second phase shift device shifts the phase of the first clock signal and outputs a second clock signal. The first output pad outputs the first clock signal. The controllable pad is controlled to selectively act as an input pad for receiving the external signal, or act as a second output pad for transmitting the second clock signal.
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What is claimed is: 1. A semiconductor chip which is capable of mounting on a printed circuit board, comprising: a signal generating circuit for generating a first signal, a second signal and a third signal; a first output node for transmitting the first signal; a second output node for transmitting the second signal; and a third output node for transmitting the third signal; wherein the second output node is utilized for connecting a terminator device mounted on the print…
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