Vertical-transport field-effect transistor with backside gate contact
US-2024105610-A1 · Mar 28, 2024 · US
Electronic device and method for fabricating the same
US9105840B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105840-B2 |
| Application number | US-201414199915-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 6, 2014 |
| Priority date | Sep 25, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.
First claim
Opening claim text (preview).
What is claimed is: 1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: a variable resistance pattern disposed over a substrate and extending in a first direction, the variable resistance pattern having a first side surface and a second side surface opposite to the first side surface in a second direction that crosses the first direction; a first structure comprising a plurality of interlayer dielectric layers and a plurality…
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- H10D84/016Primary
Electricity · mapped topic
Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9105840B2 cover?
- According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the varia…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D84/016. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).