Logic drive using standard commodity programmable logic ic chips comprising non-volatile random access memory cells
US-2024380401-A1 · Nov 14, 2024 · US
US9105839B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105839-B2 |
| Application number | US-201414333180-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 16, 2014 |
| Priority date | Dec 21, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
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What is claimed is: 1. A method of fabricating a spin torque transfer memory (STTM) array, the method comprising: forming a plurality of load line lower portions in a dielectric layer disposed above a substrate, each of the load line lower portions coupled to a corresponding transistor contact; forming a first plurality of STTM devices, one device for each of alternating ones of the plurality of load line lower portions; forming a plurality of load line upper portions, one upp…
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