Substrate correction device, substrate lamination device, substrate processing system, substrate correction method, substrate processing method, and semiconductor device manufacturing method
US-2024404859-A1 · Dec 5, 2024 · US
US9105827B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105827-B2 |
| Application number | US-201414322787-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 2, 2014 |
| Priority date | Nov 29, 2011 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.
Opening claim text (preview).
What is claimed is: 1. A layer stack for use in the manufacture of a semiconductor device, comprising: a first substrate; a semiconductor device layer on a front surface of the first substrate; a first bonding stack of one or more metal la ers on toy of the semiconductor device layer; a second bonding stack of one or more metal layers on a front surface of a second substrate; a metal stress compensation layer on a back surface of the second substrate; and a metal bond be…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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