Method for bonding semiconductor substrates

US9105827B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105827-B2
Application numberUS-201414322787-A
CountryUS
Kind codeB2
Filing dateJul 2, 2014
Priority dateNov 29, 2011
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal bonding layer or a stack of metal layers on the front surface of the second substrate, depositing a metal stress-compensation layer on the back side of the second substrate, thereafter establishing a metal bond between the first and second substrate, by bringing the first and second metal bonding layers or stacks of layers into mutual contact under conditions of mechanical pressure and temperature suitable for obtaining the metal bond, and removing the first substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A layer stack for use in the manufacture of a semiconductor device, comprising: a first substrate; a semiconductor device layer on a front surface of the first substrate; a first bonding stack of one or more metal la ers on toy of the semiconductor device layer; a second bonding stack of one or more metal layers on a front surface of a second substrate; a metal stress compensation layer on a back surface of the second substrate; and a metal bond be…

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What does patent US9105827B2 cover?
A method is provided for bonding a first substrate carrying a semiconductor device layer on its front surface to a second substrate. The method comprises producing the semiconductor device layer on the front surface of the first substrate, depositing a first metal bonding layer or a stack of metal layers on the first substrate, on top of the semiconductor device layer, depositing a second metal…
Who is the assignee on this patent?
Imec
What technology area does this patent fall under?
Primary CPC classification H10P10/128. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).