Method for manufacturing a field effect transistor of a non-planar type

US9105746B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105746-B2
Application numberUS-201414521083-A
CountryUS
Kind codeB2
Filing dateOct 22, 2014
Priority dateOct 22, 2013
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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Abstract

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A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

First claim

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What is claimed is: 1. A method for manufacturing a field effect transistor of a non-planar type, comprising: providing a substrate having an initially planar front main surface; providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures, wherein top surfaces of the shallow trench isolation structures and the fin structures are abutting on a c…

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What does patent US9105746B2 cover?
A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isola…
Who is the assignee on this patent?
Imec Vzw
What technology area does this patent fall under?
Primary CPC classification H10D64/017. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).