Semiconductor devices having a seal ring
US-2024413245-A1 · Dec 12, 2024 · US
Method of replacement source/drain for 3D CMOS transistors
US9105741B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105741-B2 |
| Application number | US-201213614062-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 13, 2012 |
| Priority date | Sep 13, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor structure comprising: providing a buried oxide layer having a surface; forming, on the surface of the buried oxide layer, at least one fin having sidewalls; forming, over a first portion of the at least one fin structure, a gate structure having sidewalls, wherein a channel region is located under the gate structure within the first portion of the at least one fin; forming gate spacers on the sidewalls of the gate st…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105741B2 cover?
- A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed …
- Who is the assignee on this patent?
- Chan Kevin K, Li Jinghong, Park Dae-Gyu, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0128. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).