SONOS type stacks for nonvolatile changetrap memory devices and methods to form the same

Patent metadata

Field	Value
Publication number	US-9105740-B2
Application number	US-201314105041-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	May 15, 2008
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

First claim

What is claimed is:

1. A nonvolatile charge trap memory device, comprising:
a tunnel dielectric layer on a surface of a substrate, the tunnel dielectric layer comprising a nitrided first oxide layer formed by a first decoupled plasma nitridation process;
a charge-trapping layer on the tunnel dielectric layer; and
a blocking dielectric layer on the charge-trapping layer, the blocking dielectric layer formed by a second decoupled plasma nitridation process.…

Assignees

• Cypress Semiconductor Corp

Inventors

• Puchner Helmut
• Polishchuk Igor
• Levy Sagy Charel

Classifications

• H10D64/685

  Electricity · mapped topic

• H10D64/037

  Electricity · mapped topic

• H10D30/694

  Electricity · mapped topic

• H10D30/69

  Electricity · mapped topic

• H10D30/0413 Primary

  Electricity · mapped topic