Three-dimensional nonvolatile memory devices including interposed floating gates

Patent metadata

Field	Value
Publication number	US-9105736-B2
Application number	US-201414164408-A
Country	US
Kind code	B2
Filing date	Jan 27, 2014
Priority date	Mar 19, 2009
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

First claim

What is claimed is:

1. A three-dimensional nonvolatile memory device, comprising:
a stacked structure including a plurality of conductive layers and insulating layers which are stacked alternately and repeatedly on a substrate;
a plurality of channel pillars penetrating the stacked structure to be connected to the substrate; and
a plurality of data storage layers disposed between the conductive layers and the channel pillars and surrounding the channel pillars;
wherein the d…

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Byoungkeun
• Kim Hansoo
• Kim Jinho
• Kim Kihyun

Classifications

• H10D64/011 Primary

  Electricity · mapped topic

• H10D30/68

  Electricity · mapped topic

• H10D30/63

  Electricity · mapped topic

• H10D30/025 Primary

  Electricity · mapped topic

• H10D88/00

  Electricity · mapped topic