Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
Thin film transistor array substrate and manufacturing method thereof
US9105733B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105733-B2 |
| Application number | US-201313897879-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 20, 2013 |
| Priority date | Jan 14, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.
First claim
Opening claim text (preview).
What is claimed is: 1. A substrate, comprising: gate wirings comprising a gate line and a gate electrode disposed on a substrate; a gate insulating layer disposed on the gate wirings; an oxide semiconductor layer pattern disposed on the gate insulating layer; data wirings comprising a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern and a drain electrode disposed on another side of the oxide semiconductor laye…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D86/60Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9105733B2 cover?
- A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electro…
- Who is the assignee on this patent?
- Samsung Display Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D86/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).