Multi-gate thin-film transistor

US9105728B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105728-B2
Application numberUS-201213557039-A
CountryUS
Kind codeB2
Filing dateJul 24, 2012
Priority dateJul 24, 2012
Publication dateAug 11, 2015
Grant dateAug 11, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.

First claim

Opening claim text (preview).

What is claimed is: 1. A device comprising: a substrate; a thin-film semiconducting layer over the substrate; a drain coupled to the semiconducting layer and capable of receiving an input signal; a source coupled to the semiconducting layer and capable of providing an output signal; a first gate electrode adjacent a first portion of the semiconducting layer between the drain and the source, the first gate electrode capable of receiving a first control signal, the first gat…

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What does patent US9105728B2 cover?
This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and config…
Who is the assignee on this patent?
Hong John Hyunchul, Kim Cheonhong, Fung Tze-Ching, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10D30/6734. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).