Semiconductor-on-insulator device including stand-alone well implant to provide junction butting

Patent metadata

Field	Value
Publication number	US-9105725-B2
Application number	US-201414154538-A
Country	US
Kind code	B2
Filing date	Jan 14, 2014
Priority date	Sep 11, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths.

First claim

What is claimed is:

1. A method of forming a semiconductor device including a semiconductor substrate, the method comprising:
forming a masking layer on an active semiconductor layer of the semiconductor substrate, the semiconductor substrate including a bulk substrate layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer;
designating at least one source/drain (S/D) area of the semiconductor substrate;
patterning the…

Assignees

• IBM

Inventors

• Guo Dechao
• Haensch Wilfried E
• Wang Gan
• Wang Xin
• Wang Yanfeng
• Wong Keith Kwong Hon

Classifications

• H10D30/0323 Primary

  Electricity · mapped topic

• H10D30/6719

  Electricity · mapped topic

• H10D30/6717

  Electricity · mapped topic

• H10D30/6715

  Electricity · mapped topic

• H10D30/6713

  Electricity · mapped topic