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Butted SOI junction isolation structures and devices and method of fabrication
US9105718B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105718-B2 |
| Application number | US-201414224384-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 25, 2014 |
| Priority date | Nov 10, 2010 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
First claim
Opening claim text (preview).
What is claimed is: 1. A structure, comprising: a silicon layer on a buried oxide layer of a silicon-on-insulator substrate; a first gate electrode of a field effect transistor on a top surface of a gate dielectric layer formed on a top surface of said silicon layer and a second gate of a second field effect transistor on said top surface of said gate dielectric layer; a trench in said silicon layer between said first and second gate electrodes, said trench extending from a to…
Assignees
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Classifications
- H10W10/0148Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/657Primary
Electricity · mapped topic
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- What does patent US9105718B2 cover?
- A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX l…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10W10/0148. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).