Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9105709-B2
Application number	US-201314055615-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Sep 8, 2011
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A semiconductor device according to the present embodiment includes a semiconductor substrate having a first n-type silicon carbide layer and a second n-type silicon carbide layer, a first p-type impurity region formed in the n-type silicon carbide layer, a first n-type impurity region of 4H-SiC structure formed in the n-type silicon carbide layer, a second n-type impurity region of 3C-SiC structure formed in the n-type silicon carbide layer having a depth shallower than the first n-type impurity region, a gate insulating film, a gate electrode formed on the gate insulating film, and a metallic silicide layer formed above the first n-type impurity region and having a bottom portion and a side surface portion such that the second n-type impurity region is sandwiched between the first n-type impurity region and at least the side surface portion.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a p-type silicon carbide layer and an n-type silicon carbide layer on the p-type silicon carbide layer;
a first p-type impurity region formed in the n-type silicon carbide layer;
a first n-type impurity region of 4H-SiC structure formed in the n-type silicon carbide layer;
a second n-type impurity region of 3C-SiC structure formed in the n-type silicon carbide layer and having a depth…

Assignees

• Toshiba Kk

Inventors

• Tsuchiya Yoshinori

Classifications

• H10P30/2042

  Electricity · mapped topic

• H10P30/21

  Electricity · mapped topic

• H10D64/0115

  Electricity · mapped topic

• H10D12/032

  Electricity · mapped topic

• H10D30/0291

  Electricity · mapped topic