Method of forming interconnection lines

Patent metadata

Field	Value
Publication number	US-9105699-B2
Application number	US-201414167065-A
Country	US
Kind code	B2
Filing date	Jan 29, 2014
Priority date	Jan 31, 2013
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

The invention concerns a method comprising: forming a plurality of parallel lines ( 502, 504, 506 ) of a sacrificial material over a layer of conductive material ( 510 ) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening ( 516 ) dividing it into first and second line portions ( 504 A, 504 B) separated by a space (S); forming spacers ( 522, 524, 526, 528, 530 ) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines ( 302, 304 A, 304 B, 306 A, 306 B, 308, 310 ) of said conductive material based on a pattern defined by said spacers.

First claim

The invention claimed is:

1. A method comprising:
forming a plurality of parallel lines in an upper mask layer, the upper mask layer being over and in contact with a lower mask layer, and the lower mask layer being over a layer of conductive material of an integrated circuit, said plurality of parallel lines being separated by trenches,
forming an opening dividing at least one of the plurality of parallel lines into first and second line portions separated by a space;
forming…

Assignees

• St Microelectronics Crolles 2

Inventors

• Farys Vincent

Classifications

• H10P76/4088

  Electricity · mapped topic

• H10P76/4085

  Electricity · mapped topic

• H10P50/71

  Electricity · mapped topic

• H10W20/063

  Electricity · mapped topic

• H10W20/43

  Electricity · mapped topic